1. Field of Invention
The present invention relates to a double diffused drain metal oxide semiconductor (DDDMOS) device and a manufacturing method thereof; particularly, it relates to such DDDMOS device and manufacturing method wherein the breakdown voltage is increased and the band-to-band tunneling effect is mitigated.
2. Description of Related Art
FIGS. 1A-1C show a cross-section view, a 3D (3-dimensional) view, and a top view of a prior art double diffused drain metal oxide semiconductor (DDDMOS) device 100, respectively. As shown in FIGS. 1A and 1B, a field oxide layer 12 is formed in a P-type substrate 11. The field oxide layer 12 for example is a shallow trench isolation (STI) structure or a local oxidation of silicon (LOCOS) structure, the former being shown in the figures. The DDDMOS device 100 includes a gate 13, a drift region 14, a source 15, and a drain 16. The drift region 14, source 15 and the drain 16 are formed by lithography processes and ion implantation processes, wherein the lithography process defines the implantation region by a photoresist mask together with a self-alignment effect provided by all or part of the gate 13, and the ion implantation implants N-type impurities to the defined region in the form of accelerated ions. The source 15 and the drain 16 are beneath the gate 13 and at different sides thereof respectively. The drift region 14 is located at the same side of the drain 16, and part of the drift region 14 is beneath the gate 13. FIG. 1C is a top view of the DDDMOS device 100 showing the relative locations of the aforementioned regions of the DDDMOS device 100, and further showing the relative locations of a conductive plug 18 and a first metal layer 19. As shown in FIG. 1C, in order to reduce the antenna effect, the locations of the conductive plug 18 and the first metal layer 19 are located outside a device region 12a (indicated by a thick border) which is defined by the field oxide layer 12 surrounding the DDDMOS device 100.
The DDDMOS device is a high voltage device designed for applications requiring higher operation voltages. However, if it is required for the DDDMOS device to be integrated with a low voltage device in one substrate, the DDDMOS device and the low voltage device should adopt the same manufacturing process steps with the same ion implantation parameters, and thus the flexibility of the ion implantation parameters for the DDDMOS device is limited; as a result, the DDDMOS device will have a lower breakdown voltage at the junction between the p-type substrate 11 and a side of the n-type drift region 14. Besides, when the DDDMOS device 100 operates in a high electric field, the energy band is bended, such that carriers with sufficient energy may tunnel from the conduction band to the valance band at the junction depletion region when the conduction band and the valance band are close enough, i.e., the leakage current induced by the band-to-band tunneling (BTBT) effect will greatly increase. As the device dimension keeps decreasing, the leakage current induced by the BTBT effect is not ignorable. Therefore, the application range of the DDDMOS device is limited under such process condition. To increase the breakdown voltage and to mitigate the BTBT effect of the DDDMOS device, additional manufacturing process steps are required, that is, at least an additional lithography process and an additional ion implantation process are required in order to provide different ion implantation parameters, but this increases the cost. FIGS. 2A and 2B respectively show simulated level contours and current-voltage characteristics of a prior art 6V DDDMOS device in a reversely biased condition. As shown in FIG. 2B, the prior art 6V DDDMOS device has a breakdown voltage around 18.7V, and the BTBT effect induced leakage current is obvious when the operation voltage is higher than 16.5V at reversely biased condition. A comparison between this prior art and the present invention having the same operation voltage (6V) will be illustrated later.
In view of above, to overcome the drawbacks in the prior art, the present invention proposes a DDDMOS device and a manufacturing method thereof which increases the breakdown voltage and mitigates the BTBT effect so that the DDMOS device may have a broader application range, in which additional manufacturing process steps are not required such that the DDDMOS device can be integrated with and a low voltage device and manufactured by common manufacturing process steps.